In this talk, I will describe examples of how advances and peculiarities of the flash storage system architecture are spurring changes in the OS. These examples include the introduction of and support for multiple queues (in software and hardware) and passing of data's lifetime information from the host down to a storage device. I will also describe our recent work to build an end-to-end system for in-storage computing - an idea that takes storage devices as continuum of compute resources.

Sangyeun Cho received the BS degree in computer engineering from Seoul National University in 1994 and the PhD degree in computer science from the University of Minnesota in 2002. In 1999, he joined the System LSI Division of Samsung Electronics Co. and contributed to the development of Samsung's flagship embedded processor core family CalmRISC(TM). He was a lead architect of CalmRISC-32, a 32-bit microprocessor core, and designed its memory hierarchy including caches, DMA, and stream buffers. In 2004, he joined the faculty of the Computer Science Department at the University of Pittsburgh and was promoted to the rank of tenured associate professor in 2010. He has joined Samsung’s Memory Division in 2012 to lead systems-related technical initiatives, where he is a VP for advanced solutions research and development. His research interests are in the area of computer architecture and systems with particular focus on performance, power and reliability of memory and storage hierarchy design for next-generation data centers.