While deep learning is getting ever more popular across industries and in academia, the� enormous computational challenge of deep learning calls for new research into efficient hardware acceleration of the emerging workload. In particular, FPGAs are a very interesting platform for deep learning applications, as it combines hardware parallelism and software flexibility in a unique way. In this talk I will discuss new challenges of mapping state-of-the-art binarized neural networks to FPGAs.

Contrary to general perception that Binarized Neural Networks (BNN) are a good fit for FPGAs, conventional BNNs have an significant drawback---they tend to have much lower recognition performance compared with their non-binarized counterparts, especially when used for large datasets. Local Binary Convolutional Neural Network (LBCNN) addresses this problem, providing both high recognition performance and lower computational complexity. LBCNN (as well as other scalable, accurate BNNs) achieves this by combining binarized computation and non-binarized computation within a single layer, but this hybrid structure of LBCNN layers poses a new challenge when it comes to FPGA mapping. In this talk we discuss the core problems and proposed solutions, and how we can reap the benefit of advanced network models on FPGAs. This work also provides an opportunity to quantitatively measure hardware implementation efficiency on FPGA between binarized vs. non-binarized DNNs.

Jongeun Lee is an associate professor at the School of Electrical and Computer Engineering at� the Ulsan National Institute of Science and Technology (UNIST).

After receiving his doctorate in EECS at Seoul National University in 2004, he joined the the SoC R&D Center at Samsung Electronics as a senior engineer. From 2007 to 2009, he worked as a PostDoc at the Arizona State University with Prof. Aviral Shrivastava, working on heterogeneous multicore architectures and compiler techniques for reconfigurable computing.

Jongeun Lee’s current focus of research is in the area of digital and semi-digital neural network processors, reconfigurable processors, hardware-software co-optimization, and emerging technologies and their applications to reconfigurable and neuromorphic systems. Recent publications include “FPGA Implementation of CNN Based on Stochastic Computing”, “Accurate and Efficient Stochastic Computing Hardware for CNN” and “Computing Multiplier with Application to Deep CNN”.