Probabilistic modeling and inference is an important class of machine learning, widely used for unsupervised or semi-supervised learning tasks. While successful deep learning models depend on large labeled data sets, probabilistic methods, in particular Bayesian methods, excel on problems with limited or no data for training and those that require representation and manipulation of uncertainties. One of the challenges when deploying Bayesian methods is the large amount of computation required to process high-dimensional integrals. As the number of parameters increase, the inference on these models often become intractable, which motivates a specialized hardware accelerator to enable energy-efficient real-time performance. Research test chips are the ultimate experiment to demonstrate the true value of such novel architecture innovations. However, taping out test chips remains a challenge in research settings; it is time consuming to design, fabricate and test, and often error prone - potentially requiring re-spins to fix problems. In this talk, we present the programmable Bayesian inference accelerator for unsupervised machine perception in 16nm FinFET, which is designed leveraging CHIPKIT, an agile open-source framework for robust research test chips, significantly reducing the overhead of taping out and testing the SoC. The accelerator is capable of running tasks mapped onto a 2D Markov Random Field, a probabilistic graphical model, via Markov Chain Monte Carlo based Bayesian inference. With two levels of parallelism, it performs Gibbs sampling inference to achieve up to 1375x speedup and 1958x energy efficiency versus Arm A53, while running at 450 MHz on 0.8 V, producing 44.6 Msamples/s at 0.88 nJ/sample.

Glenn Gihyun Ko is a postdoctoral researcher at Harvard University working with Professor Gu-Yeon Wei and Professor David Brooks. He received B.S. and M.S. in Electrical and Computer Engineering, both from the University of Illinois at Urbana-Champaign in 2004 and 2006 respectively. He then joined Samsung Electronics and engaged in research and development of Exynos application processor SoCs. He returned to Illinois and received Ph.D. in Electrical and Computer Engineering in 2017 before joining Harvard University in 2018. He has also spent summers at Qualcomm Research and IBM Research on machine learning and architecture research. His current research interests are machine learning, algorithm-hardware co-design and scalable accelerator architectures on the cloud and edge devices.