The main memory systems have gone through dramatic in-creases in bandwidth and capacity over technology generations. In contrast, their random access latency has remained relatively constant. For given memory technology, optimizing the latency typically requires sacrificing the total capacity and density (i.e., cost per bit), which are the two most critical concerns for memory industry. Therefore, recent studies have proposed memory architecture comprised of asymmetric (fast, low-capacity and slow, high-capacity) regions to optimize between overall latency and negative impact on the capacity and density. Such memory architecture, however, presents a unique challenge, requiring frequently-accessed pages to be placed in the fast region. Otherwise, an expensive page migration is required. In this paper, we propose a novel memory architecture sharing a set of row buffers between a pair of neighboring banks for resistive memories. This shared row-buffer architecture enables two techniq ues. First, the shared row buffers provide a vehicle for migrating pages between slow and fast banks with minimal overhead. Second, the shared row buffers can be dynamically partitioned between the two banks based on the memory access patterns, i.e., allocating more row buffers to busy banks. With an asymmetric memory architecture that aims to increase capacity with high-density slow banks while maintaining high performance with low-density fast banks, our shared row-buffer architecture can help capture 94%~97% of the potential performance of a memory architecture comprised of only fast banks.

I am an Associate Professor at the University of Illinois, Urbana-Champaign and an IEEE Fellow. I have been conducting interdisciplinary research that cuts across device, circuit, and architecture for power-efficient computing. Prior to joining the University of Illinois, I was a faculty member at the University of Wisconsin, Madison (2008--2015) and a Senior Research Scientist/CPU Architect at Intel (2004 -- 2008), where I conducted research in power-efficient digital circuit and process architecture. I have published nearly 130 refereed articles in highly-selective conferences and journals in the field of digital circuit, processor architecture, and computer-aided design. My top five most frequently cited papers have more than 2900 combined citations and the total number of combined citations for all my papers is nearly 5200. I have also served several prominent international conferences and a journal such as IEEE/ACM International Symposium on Computer Architecture (ISCA), I EEE/ACM International Symposium on Computer Microarchitecture (MICRO), IEEE/ACM International Symposium on High-Performance Computer Architecture (HPCA), IEEE/ACM Design Automation Conference (DAC), and ACM Transactions on Design Automation of Electronic Systems as a technical program committee and an associate editor. I was a recipient of the IEEE Design Automation Conference (DAC) Student Design Contest Award in 2001, Intel Fellowship in 2002, IEEE International Symposium on Microarchitecture (MICRO) Best Paper Award in 2003, NSF CAREER Award in 2010, and IBM Faculty Award in 2011 and 2012, and University of Wisconsin Villas Associates Award in 2015. I am the first Korean member of IEEE/ACM International Symposium on High-Performance Computer Architecture (HPCA) Hall of Fame. Recognizing my exceptional achievements, the department awarded me the early tenure in 2013 –the first early tenure case approved by the department in more than 10 years. I hold a Ph.D. in Computer Science and Engineering from the University of Michigan, Ann Arbor and a Master and Bachelor’s degree in Electrical Engineering from Korea Advanced Institute of Science and Technology.