As transistor sizes continue to scale, we are about to witness stunning levels of chip integration, with 1,000 cores on a single die, and increasing levels of die stacking. Transistors may not be much faster, but there will be many more of them. In these architectures, efficient communication and synchronization will be a challenge. Moreover, energy and power will constrain the designs even more than they do today.In this context, this talk presents some of the technologies that we may need to deploy to exploit these architectures. To enable data sharing, we need novel synchronization and fence hardware. For low-latency communication, we may leverage on-chip wireless networks. Cores need to be voltage scalable--i.e., flexibly operate both at high and low voltage ranges. Techniques for efficient energy use need to be widespread. Finally, hardware extensions to ease programming will provide a competitive edge. A combination of all of these techniques--and more--are needed.

Josep Torrellas is the Saburo Muroga Professor of Computer Science at the University of Illinois at Urbana-Champaign. He is a Fellow of IEEE and ACM. He is the Director of the Center for Programmable Extreme-Scale Computing, a center focused on architectures for extreme energy and power efficiency. He was until recently the Director of the Intel-Illinois Parallelism Center (I2PC), a center created by Intel to advance parallel computing. He has made contributions to parallel computer architecture in the areas of shared memory multiprocessor organizations, cache hierarchies and coherence protocols, thread-level speculation, and hardware and software reliability. He received the 2015 IEEE CS Technical Achievement Award.